在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
EETOP诚邀模拟IC相关培训讲师 创芯人才网--重磅上线啦!
查看: 39981|回复: 191

[原创] [文集] Signal Integrity Characterization Techniques Resso & Bogatin 2009

[复制链接]
发表于 2010-5-10 06:24:24 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
本帖最后由 calabazas 于 2010-12-10 09:31 编辑

[文集] Signal Integrity Characterization Techniques 2009

求人不如求己,拼凑集种,就差第17章的5页 (569,571,574,575,578) ,有劳有心的朋友帮忙补齐


Cover.jpg

[Description]

Signal Integrity Characterization Techniques addresses the gap between traditional digital and microwave measurement technologies while focusing on a practical and intuitive understanding of signal integrity effects within the data transmission channel. High-speed interconnects such as connectors,
PCBs, cables, IC packages, and backplanes are critical elements of differential channels that must now be optimized using today’s most powerful analysis and characterization tools. Both measurements and simulation must be done on the device under test and must yield data that correlates with each other. Most of this book focuses on real-world applications of signal integrity measurements—from backplane design challenges to advanced error correction techniques to jitter measurement tools. The authors’ approach wisely address many of today’s high-speed technologies, provides excellent insight into its future direction, and will teach the reader valuable lessons pertaining to the signal integrity industry.

ABOUT THE AUTHORS

Mike Resso is a signal integrity application specialist in the component test division of Agilent Technologies. He is responsible for the technical training of field engineers, symposium lecturing, and the creation of sales tools that will expand the worldwide market growth of high bandwidth oscilloscopes. His current activities include developing novel signal integrity measurement techniques related to high-speed digital design applications, identifying new test methodologies in the communications field, and interfacing with Agilent R&D engineers to bring innovative products to the marketplace. He has over twenty years experience in the test and measurement industry, and his background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications. His most recent activity has focused on the complete multiport characterization of high speed digital interconnects using time domain reflectometry and vector network analysis. He has authored over 20 technical papers in diverse fields such as infrared detector probe systems, linearly variable optical filters, and electrically conductive antireflection coatings. Mike received a B.S. degree in electrical and computer engineering from University of California.

Eric Bogatin is signal integrity evangelist of Bogatin Enterprises, LLC which specializes in training for signal integrity and interconnect design. His company offers a complete curriculum in short courses and training materials to help accelerate engineers and managers up the learning curve to be more effective in fields related to signal integrity. He has held senior engineering and management positions at such companies as AT&T Bell Labs, Raychem Corporation, Advanced Packaging Systems, and Sun Microsystems. For 20 years, he has been involved in various aspects of signal integrity and inter-connect design, from the materials side, manufacturing, product design, measurements and, most recently, education and consulting. Eric has written four books on signal integrity and inter-connect design, over 200 papers, and most recently wrote a book entitled Signal Integrity-Simplified published in 2004. Eric received his Ph.D. in physics from the University of Arizona in Tucson in 1980 and his B.S. in physics from the Massachusetts Institute of Technology in 1976.

[Contents]

Part I: Getting Started – Introducing TDR and VNA Techniques and the Power of S-Parameters

Chapter 1: Signal-Port TDR, TDR/TDT, and Two-Port TDR: Interconnect Analysis is Simplified with Physical Layer Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies

Chapter 2: 4-Port TDR/VNA/PLTS – Interconnect Analysis Is Simplified with Physical Layer Test Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies

Chapter 3: Differential Impedance Design and Verification with Time Domain Reflectometry
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies

Chapter 4: Utilizing TDR and VNA Data to Develop Four-Port Frequency-Dependent Models
Jim Mayrand, Signal Integrity Consultant
Mike Resso, Product Manager, Signal Integrity Operation, Agilent Technologies
Dima Smolyansky, TDA Systems

Chapter 5: Accuracies and Limitations of Time and Frequency Domain Analyses of Physical-Layer Devices
Robert Schaefer, Technical Leader and R&D Project Manager, Signal Integrity Group, Agilent Technologies

Chapter 6: Data Mining 12-Port S-Parameters
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies

Part II: Backplane Measurements and Analysis

Chapter 7: A Design of Experiments for Gigabit Serial Backplane Channels
Jack Carrel, System IO Specialist,
Xilinx
Bill Dempsey, Owner and President, Redwire Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies

Chapter 8: Gigabit Backplane Design, Simulation, and Measurement: The Unabridged Story
Edward Sayre, Owner and Director, NESA
Jinhua Chen, Signal Integrity and EMI Engineer, NESA
Michael Baxter, Signal Integrity Engineer, NESA
Gautam Patel, Signal Integrity Engineer, New Product Development, Teradyne
John Goldie, Member of the Technical Staff, National Semiconductor
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies

Part III: Assuring Quality Measurements = Probing and De-Embedding

Chapter 9: The ABCs of De-Embedding
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies

Chapter 10: Backplane Differential Channel Microprobe Characterization in Time and Frequency Domains
Eric Bogatin, Chief Technologial Officer, GigaTest Labs
Mike Resso, Signal Integrity Operation, Agilent Technologies

Chapter 11: Differential PCB Structures Using Measured TRL Calibration and Simulated Structure De-Embedding
Heidi Barnes, High-Frequency Device Interface Board Designer, Verigy, Inc.
Antonio Ciccomancini, Application Engineer, CST of America, Inc.
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
Ming Tsai, Staff Hardware Development Engineer, Production Technology Division, Xilinx

Chapter 12: Validating Transceiver
FPGAs Using Advanced Calibration Techniques
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Hong Shi, Member of Technical Staff, Packing Technology,
Altera

Chapter 13: Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the DUT Socket
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Michael Comai, Senior Product Engineer, AMD
Abraham Islas, Senior Product Engineer, AMD
Francisco Tamayo-Broes, Product Development Engineer, AMD
Mike Resso, Signal Integrity Measurement Specialist, Component Test Division, Agilent Technologies
Antonio Ciccomancini, Application Engineer, CST
Orlando Bell, Vice President, Engineering, GigaTest Labs
Ming Tsai, Principal Engineer, RF Design Group, Amalfi Semiconductor

Chapter 14: Frequency Domain Calibration: A Practical Approach for the Serial Data Designer
Steven Corey, Principal Engineer, Electro-Optical Product Line, Tektronix
Eric Bogatin, President, Bogatin Enterprises
Dima Smolyansky, Product Marketing Manager, Tektronix

Chapter 15: Practical Design and Implementation of Stripline TRL Calibration Fixtures for 10-Gigabit Interconnect Analysis
Vince Duperron, Design Engineer, Molex
Dave Dunham, Electrical Engineer Manager, Molex
Mike Resso, Product Manager, Signal Integrity Applications, Agilent Technolgies

Part IV: Jitter and Active Signal Analysis

Chapter 16: Channel Compliance Testing Utilizing Novel Statistical Eye Methodology
Anthony Sanders, Principal Engineer, Infineon
Mike Resso, Product Manager, Agilent Technologies
John D’Ambrosia, Manager, Semiconductor Relations, Tyco Electronics

Chapter 17: Characterizing Jitter Performance on High-Speed Digital Devices Using Innovative Sampling Technology
Osvaldo Buccafusca, Development Scientist, Lightwave Division, Agilent Technologies
Mike Resso, Product Manager, Agilent Technologies

Chapter 18: Signal Integrity Concerns When Modulating Laser Transmitters at Gigabit Rates
Stephen Reddy, Senior Design Engineer, Transmission Subsystems Group, JDS Uniphase
Laurie Taira, Senior Product Engineer, Research and Development, Delphi Connection Systems
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies

Part V: Analysis of New Technologies

Chapter 19: The Role of Dielectric Constant and Dissipation Factor Measurements in Multi-Gigabit Systems
Eric Bogatin, President, Bogatin Enterprises
Shelley Begley, Team Leader, Agilent Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies

Chapter 20: Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced Verification Methodologies
Kevin Grundy, Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Business Development Manager, Signal Integrity Operation, Agilent Technologies

Chapter 21: Investigating Microvia Technology for 10 Gbps and Higher Telecommunications Systems
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland Mödinger, Senior Engineer, ERNI Electroapparate GmbH
Jason Roe, Application Engineer, ERNI Electroapparate GmbH

Chapter 22: ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Tom McCarthy, Vice President, Taconic
William Burns, Senior Applications Engineer, Altanova Corporation
Crescencio Gutierrez, Engineering and Research and Development Manager, Harbor Electronics
Mike Resso, Signal Integrity Measurement Specialist, Agilent Technologies

Part VI: Future Directions

Chapter 23: Design and Test Challenges Facing Next-Generation 20 Gbps Interconnects
Jay Diepenbrock, Senior Technical Staff Member, Interconnect Qualification Engineering, IBM
Will Miller, Vice President, Engineering, Efficere Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies

Author Biographies



由于多位网友反映档案太小, 且分包不足4.5MB, 所以附件已删除
若有不介意, 愿意多花个5信元的, 可向斑竹反应
没必要好心分享还遭闲话或是删帖


 楼主| 发表于 2010-5-10 06:48:26 | 显示全部楼层
本帖最后由 calabazas 于 2010-12-10 09:00 编辑

这个档名中"&"上载后被改成"&"
下载后还原档名即可解压
发表于 2010-5-10 07:52:49 | 显示全部楼层
loook
发表于 2010-5-10 09:12:04 | 显示全部楼层
下来看看,谢谢。
发表于 2010-5-10 13:11:22 | 显示全部楼层
下来一LOOK
发表于 2010-5-10 13:28:23 | 显示全部楼层
Thanks for your shareing !!!
发表于 2010-5-10 15:58:23 | 显示全部楼层
好东西,有背板设计的
发表于 2010-5-10 16:02:48 | 显示全部楼层
没有顺序命名?
 楼主| 发表于 2010-5-10 16:27:45 | 显示全部楼层
本帖最后由 calabazas 于 2010-5-10 16:46 编辑


有啊!
part01在一楼,那不是依顺序排得好好的,二楼档名中"&"上载后被改成"&"amp;
下载后还原档名即可解压
发表于 2010-5-10 17:21:35 | 显示全部楼层
好东西,有背板设计的
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-25 12:22 , Processed in 0.032584 second(s), 11 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表