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【图书】80486 System Architecture ,pdf 有目录,认为是就请多顶下!!!

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发表于 2009-11-1 17:30:25 | 显示全部楼层 |阅读模式

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x
About This Book
The MindShare Architecture Series.......................................................................................1
Organization of This Book.......................................................................................................2
Who Should Read This Book..................................................................................................3
Prerequisite Knowledge...........................................................................................................4
Documentation Conventions...................................................................................................4
Hex Notation........................................................................................................................4
Binary Notation....................................................................................................................4
Decimal Notation.................................................................................................................4
Signal Name Representation..............................................................................................5
Identification of Bit Fields...................................................................................................5
We Want Your Feedback..........................................................................................................5
E-Mail/Phone/FAX............................................................................................................5
Bulletin Board.......................................................................................................................6
Mailing Address..................................................................................................................6
Chapter 1: 80486 Overview
System Performance Prior to the 80486..................................................................................7
The Memory Bottleneck...........................................................................................................7
The Static Ram, or SRAM, Solution...................................................................................8
The External Cache Solution..............................................................................................8
Advantage: Reduces Many Memory Accesses to Zero Wait States.......................8
Disadvantage: Memory Accesses Still Bound By Bus Speed..................................8
The 80486 Solution: Internal Code/Data Cache..............................................................9
Faster Memory Accesses..............................................................................................9
Frees Up the Bus...........................................................................................................9
The Floating-Point Bottleneck................................................................................................9
The 80386/80387 Solution................................................................................................10
The 80486 Solution: Integrate the FPU............................................................................10
The 80486 Microarchitecture..................................................................................................10
The Intel Family of 486 Processors.......................................................................................12
v
80486 System Architecture
Chapter 2: Functional Units
The 80486 Functional Units....................................................................................................13
Introduction........................................................................................................................13
The 80486 Bus Unit............................................................................................................15
The 80486 Cache Unit........................................................................................................15
The Instruction Pipeline/Decode Unit...........................................................................16
Instruction Prefetch....................................................................................................17
Two-Stage Instruction Decode..................................................................................18
Execution.....................................................................................................................18
Register Write-Back....................................................................................................18
The Control Unit................................................................................................................18
The Floating-Point Unit....................................................................................................19
The Datapath Unit.............................................................................................................19
The Memory Management Unit (MMU)........................................................................20
Chapter 3: The Hardware Interface
Hardware Interface..................................................................................................................21
General................................................................................................................................21
Clock..........................................................................................................................................23
Address......................................................................................................................................23
Data Bus.....................................................................................................................................24
Data Bus Parity.........................................................................................................................25
Bus Cycle Definition...............................................................................................................26
Bus Cycle Control....................................................................................................................27
Burst Control............................................................................................................................28
Interrupts...................................................................................................................................28
Bus Arbitration.........................................................................................................................29
Cache Invalidation..................................................................................................................30
Cache Control...........................................................................................................................30
Numeric Error Reporting........................................................................................................32
Bus Size Control.......................................................................................................................32
Address Mask...........................................................................................................................33
SL Technology..........................................................................................................................33
Boundary Scan Interface........................................................................................................34
Upgrade Processor Support...................................................................................................35
Chapter 4: The 486 Cache and Line Fill Operations
The 486 Caching Solution......................................................................................................37
The 486 Internal Cache......................................................................................................37
The Advantage of a Level 2 Cache..................................................................................38
The 486 with an L2 Look-Through Cache...........................................................................38
vi
Contents
Handling of I/O Reads.....................................................................................................40
Handling of I/O Writes....................................................................................................40
Handling of Memory Reads.............................................................................................40
Handling of Memory Writes............................................................................................41
Handling of Memory Reads by Another Bus Master...................................................41
When a Write-Through Policy is Used....................................................................42
When a Write-Back Policy is Used...........................................................................42
Handling of Memory Writes by Another Bus Master..................................................42
When a Write-Through Policy is Used....................................................................43
When a Write-Back Policy is Used...........................................................................43
The Bus Snooping Process.....................................................................................................45
Summary of the L2 Look-Through Cache Designs...........................................................45
The 486 with an L2 Look-Aside Cache................................................................................46
Anatomy of a Memory Read..................................................................................................48
The Internal Cache's View of Main Memory.................................................................48
L1 Memory Read Request................................................................................................49
The Structure of the L1 Cache Controller.......................................................................49
Set the Cache Stage............................................................................................................50
The Cache Look-Up...........................................................................................................52
The Bus Cycle Request......................................................................................................52
Memory Subsystem Agrees to Perform a Line Fill.......................................................54
Cache Line Fill Defined.....................................................................................................55
Conversion to a Cache Line Fill Operation....................................................................56
L2 Cache's Interpretation of the Memory Address.......................................................56
The L2 Cache Look-Up.....................................................................................................57
The Affect of the L2 Cache Read Miss on the Microprocessor....................................57
Organization of the DRAM Main Memory....................................................................57
The Cache Line Fill Transfer Sequence...........................................................................58
The First Doubleword Is Read from DRAM Memory..................................................59
First Doubleword Transferred to the L2 Cache and
the 80486 Microprocessor.................................................................................................59
Memory Subsystem's Treatment of the Next Three
Doubleword Addresses....................................................................................................60
Transfer of the Second Doubleword to the Microprocessor........................................60
Memory Subsystem Latching of the Third and Fourth Doublewords.......................61
Transfer of the Third Doubleword..................................................................................61
The Beginning of the End.................................................................................................62
Transfer of the Fourth and Final Doubleword...............................................................62
Internal Cache Update......................................................................................................62
Summary of the Memory Read........................................................................................64
Burst Transfers from Four-Way Interleaved Memory......................................................64
Burst Transfers from L2 Cache..............................................................................................66
vii
80486 System Architecture
The Interrupted Burst.............................................................................................................67
Cache Line Fill Without Bursting.........................................................................................69
Internal Cache Handling of Memory Writes......................................................................73
Invalidation Cycles (486 Cache Snooping).........................................................................73
L1 and L2 Cache Control........................................................................................................74
Chapter 5: Bus Transactions (Non-Cache)
Overview of 486 Bus Cycles...................................................................................................77
Bus Cycle Definition...............................................................................................................78
Interrupt Acknowledge Bus Cycle.......................................................................................79
Special Cycles...........................................................................................................................79
Shutdown Special Cycle...................................................................................................80
Flush Special Cycle............................................................................................................80
Halt Special Cycle..............................................................................................................80
Stop Grant Acknowledge.................................................................................................81
Write-Back Special Cycle..................................................................................................81
Non-Burst Bus Cycles.............................................................................................................81
Transfers with 8-,16-, and 32-bit Devices............................................................................82
Address Translation..........................................................................................................82
Data Bus Steering...............................................................................................................84
Non-Cacheable Burst Reads..................................................................................................85
Non-Cacheable Burst Writes.................................................................................................87
Locked Transfers......................................................................................................................89
Pseudo-Locked Transfers.......................................................................................................89
Transactions and BOFF# (Bus Cycle Restart).....................................................................90
The Bus Cycle State Machine................................................................................................91
I/O Recovery Time...................................................................................................................92
Write Buffers............................................................................................................................93
General................................................................................................................................93
The Write Buffers and I/O Cycles...................................................................................94
Chapter 6: SL Technology
Introduction to SL Technology Used in the 486 Processors.............................................95
System Management Mode (SMM).....................................................................................96
System Management Memory (SMRAM)......................................................................98
The SMRAM Address Map.......................................................................................98
Initializing SMRAM.................................................................................................101
Changing the SMRAM Base Address....................................................................101
Entering SMM..................................................................................................................101
The System Asserts SMI..........................................................................................101
Back-to-Back SMI Requests..............................................................................102
SMI and Cache Coherency...............................................................................102
viii
Contents
Pending Writes are Flushed to System Memory..................................................102
SMIACT# is Asserted (SMRAM Accessed)...........................................................103
Processor Saves Its State..........................................................................................103
Auto-HALT Restart...........................................................................................105
SMM Revision Identifier..................................................................................105
SMBASE Slot......................................................................................................106
I/O Instruction Restart.....................................................................................106
The Processor Enters SMM.....................................................................................107
Address Space...........................................................................................................108
Exceptions and Interrupts.......................................................................................108
Executing the SMI Handler............................................................................................109
Exiting SMM.....................................................................................................................109
Processor’s Response to RSM..................................................................................109
State Save Area Restored.........................................................................................110
Maintaining Cache Coherency When SMRAM is Cacheable.............................111
486 Clock Control...................................................................................................................111
The Stop Grant State........................................................................................................111
Stop Clock State...............................................................................................................113
Auto-HALT Power Down..............................................................................................113
Stop Clock Snoop State...................................................................................................114
Chapter 7: Summary of Software Changes
Changes to the Software Environment..............................................................................115
Instruction Set Enhancements.............................................................................................116
The Register Set.....................................................................................................................117
Base Architecture Registers............................................................................................117
The System-Level Registers............................................................................................119
Control Register 0 (CR0)..........................................................................................120
Cache Disable (CD) and Not Write-Through (NW).....................................121
Alignment Mask (AM)......................................................................................121
Write-Protect (WP)............................................................................................122
Numeric Exception (NE)..................................................................................122
Control Register 2 (CR2)..........................................................................................122
Control Register 3 (CR3)..........................................................................................123
Control Register 4 (CR4)..........................................................................................123
Global Descriptor Table Register (GDTR).............................................................124
Interrupt Descriptor Table Register (IDTR)..........................................................124
Task State Segment Register (TR)...........................................................................124
Local Descriptor Table Register (LDTR)................................................................124
Virtual Paging..................................................................................................................125
The Floating-Point Registers...................................................................................126
The Debug and Test Registers................................................................................128
ix
80486 System Architecture
Chapter 8: The 486SX and 487SX Processors
Introduction to the 80486SX and 80487SX Processors.....................................................131
The 486SX Signal Interface..................................................................................................132
Register Differences..............................................................................................................132
Chapter 9: The 486DX2 and 486SX2 Processors
The Clock Doubler Processors............................................................................................135
Chapter 10: The Write Back Enhanced 486DX2
Introduction to the Write Back Enhanced 486DX2..........................................................137
Advantage of the Write-Back Policy..................................................................................138
The Write-Through Policy..............................................................................................138
The Write-Back Policy.....................................................................................................139
Signal Interface......................................................................................................................139
New Signals......................................................................................................................139
Existing Signals with Modified Functionality..............................................................141
The MESI Model....................................................................................................................141
Write Back Enhanced 486DX2 System without an L2 Cache.........................................144
Cache Line Fill..................................................................................................................144
Bus Master Read — Processor Snoop...........................................................................146
Bus Master Write — Processor Snoop..........................................................................148
Write Back Enhanced 486DX2 System with an L2 Cache...............................................150
The L2 Cache with a Write-Through Policy.................................................................151
The L2 Cache with a Write-Back Policy........................................................................152
Snoop Cycle During Cache Line Fill.............................................................................152
Special Cycles.........................................................................................................................155
Clock Control..........................................................................................................................156
Chapter 11: The 486DX4 Processor
Primary Feature of the 486DX4 Processor.........................................................................159
Clock Multiplier....................................................................................................................159
16KB Internal Cache..............................................................................................................160
5vdc Tolerant Design............................................................................................................162

80486 System Architecture [3rd Edition] [1995].pdf

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发表于 2009-11-2 00:11:13 | 显示全部楼层
xiexie
发表于 2009-11-2 09:30:22 | 显示全部楼层
thanks!!!
发表于 2009-11-2 15:11:52 | 显示全部楼层
不错! 谢谢分享
发表于 2009-11-2 16:26:57 | 显示全部楼层
thanks!
发表于 2009-11-23 16:02:29 | 显示全部楼层
Thanks for your sharing!
发表于 2009-11-29 19:43:27 | 显示全部楼层
看一看
发表于 2009-11-29 19:50:41 | 显示全部楼层
谢谢lz
发表于 2009-11-29 21:30:25 | 显示全部楼层
太强了,顶
发表于 2009-12-5 03:20:05 | 显示全部楼层
3QQQQQ~~~~~
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