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Any fast method to checking floating node?

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发表于 2009-9-20 11:00:04 | 显示全部楼层 |阅读模式

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Hi Folk,

Does C@dence provide any simulation method to check floating node (hidden floating node because of circuit design) of my circuit? Could you tell me how could I do it?

Thanks

smartchi
发表于 2009-9-20 14:18:54 | 显示全部楼层
Hi, smartchi:
There are 2 phase of floating node checking:
First one is in front-end  phase:
HAL report, DC report, even elaboration warnings can give you a hint of floating node
You mentioned simulation method so I guess this should be what you want
Second one is in physical verification phase
When you do ERC checking, back-end tools can tell you if e.g. there is a transistor with floationg node.

Hope this helps
 楼主| 发表于 2009-9-21 14:10:17 | 显示全部楼层
Hi Haharun,


       Thanks for your reply. Could you tell me what is HAL? Moreover, you mention the backend method. Could you tell me more in detailed about this?

Thanks

smartchi




原帖由 haharun 于 2009-9-20 02:18 PM 发表 Hi, smartchi:There are 2 phase of floating node checking:First one is in front-end  phase:HAL report, DC report, even elaboration warnings can give you a hint of floating nodeYou mentioned sim ...

发表于 2009-9-22 06:36:39 | 显示全部楼层
I use Debussy for such a task - it have feature to report all Z's in the design in the current simulation time. They are generally good candidates for the floating net's.
Of course you can use special Lint tools - nLint, HAL, Leda, HDL Designer.
Depending on you skills - DC, Quartus could be used for better synthesys checks (bus width mismatch, drive of an input port, busses merged to single bit due to implicit wire declaration etc).
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